FPGA Design Engineer

PierSight is a young startup building the world’s largest constellation of Synthetic Aperture Radar and AIS satellites for the most extensive surveillance of oceans.

The startup is backed by Techstars Space (In collaboration with NASA and US Space Force) and a few marque investors from India. You will be a part of the Earth Observation Satellite Payload Development Team.

You will be a part Earth Observation Satellite Payload Development Team

You will develop RTL code to implement FPGA-based digital designs for the payload controller of SAR Payload. The project includes designing logic for High-Speed Data Converter interfaces, digital signal processing, and control logic (bus interfaces and state machines)

You will design the Micro-architecture and coding of the assigned module in VHDL/Verilog

You will debug code using ChipScope and other debugging techniques.

You will write a test bench for verifying the design.

You will perform FPGA debugging and HW/SW integration.

4+ years of experience in completing FPGA projects.

Coding experience in VHDL and/or Verilog is a must.

Experience targeting Xilinx and Microchip FPGAs

Implementation of designs with multiple clock domains is required.

Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed

Experience in RTL implementation of DSP algorithms will be appreciated

Experience in interfaces like JESD, UART, Aurora, DRAM, SRAM, etc.

Education: UG: Any Graduate, PG: Any Postgraduate

Write to life@piersight.space with the following: